International Journal of Advanced Computing and Communication Systems

Realization of N-Bit Fault Tolerant Division unit using Reversible Logic in QCA

Marichamy P, Department of ECE, P.S.R. College of Engineering, Sivakasi, Tamil Nadu, India.

Kamaraj A and Dhivya Bharathi J, Department of ECE, Mepco Schlenk Engineering College, Sivakasi, Tamil Nadu, India.

International Journal of Advanced Computing and Communication Systems

Received On :

Revised On :

Accepted On :

Published On :

Volume 06, Issue 02

Page No :012-017

Abstract

Reversible logic plays an important role in VLSI design. Reversible logic is a potential area of study regarding further technological innovations. It has voluminous applications in quantum computing, optical computing, Quantum Dot Cellular Automata (QCA) and digital signal processing. The major application of reversible logic is in quantum computation as the quantum circuits must be reversible. One of the important issues in reversible logic is parity preservation in which parity of inputs and outputs are equal in reversible gate. In this paper, we propose a New Reversible Fault Tolerant n-bit divider circuit where n is the number of bits of dividend and divisor. The division unit is designed with the proposed New Reversible Fault Tolerant gates, which are parity preserve. An algorithm has been used to reduce the number of steps required for performing division operation. A fault tolerant reversible divider is designed based on this algorithm. In this division circuit, we use fault tolerant reversible components like fault tolerant reversible shift register, fault tolerant reversible parallel adder, D-latch, Multiplexer, Left shift register, rounding and normalization registers. The proposed reversible gates satisfy the property of reversibility, universality and fault tolerant. Using these fault tolerant reversible gates the Quantum Cost, Garbage Outputs and Gate Counts of the design can be reduced. The entire division circuit is realized in QCA environment.

Keywords

Reversible Logic, Quantum Cellular Automata (QCA), Quantum Cost.

Cite this Article

Marichamy P, Kamaraj A and Dhivya Bharathi J, “Realization of N-Bit Fault Tolerant Division unit using Reversible Logic in QCA", International Journal of Advanced Computing and Communication Systems, pp. 001-008, July 2019.

Copyright

© 2019 Marichamy P, Kamaraj A and Dhivya Bharathi J. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.