International Journal of Advanced Computing and Communication Systems

Stimulation and Hardware Development of Frequency Reader & Bit Error Rate Using VHDL

Sudharsan S, National Remote Sensing Centre (NRSC), Indian Space Research Organization (ISRO), Hyderabad, India.

International Journal of Advanced Computing and Communication Systems

ISSN (Online) : 2347 - 9299

ISSN (Print) : 2347 - 9280

Received On :

Revised On :

Accepted On :

Published On :

Volume 04, Issue 02

Page No : 021-028

Abstract

Data communication refers to the exchange of data between a source and a receiver over a point-to-point or point-to- multipoint communication channel. Frequency is defined as the number of events of a particular sort occurring in a set period of time. Frequency counters usually measure the number of oscillations or pulses per second in a repetitive electronic signal. In this paper, we used a crystal oscillator of 10 MHz to generate the timebase. The timebase is a pulse signal which is 10 ms of High portion followed by a 0.3 µs of Low portion and this continuing periodically. When the timebase is high the counter accumulates the number of rising edge of the test signal and transfers the count value to the display as soon as the timebase becomes low and the counter is reset to zero for further counting in the next high portion of the timebase. In digital transmission, the number of bit errors is the number of receiving bits of a data stream over a communication channel that has been altered due to noise, interference, distortion or bit synchronization errors. The bit error rate (BER) is the number of bit errors per unit time. The bit error ratio (also BER) is the number of bit errors divided by the total number of transferring bits during a studied time interval. BER is a unit less performance measure. For 15 bit Pseudo Random Binary Sequence (PRBS) error detection, the technique that we’ve used compares the XOR of 15th and 16th received bit with the latest bit received. If they match, the mismatch counter remains at the same value as earlier, otherwise it increments by one. When an erroneous bit is received, that leads to error multiplication in the next stages of checking. This is so because, when the erroneous bit becomes the 15th or 16th bit that will be used for checking the incoming bit, the result to compare might be different from what it should have been actually. This leads to a maximum error reading of 3, for only a single bit received incorrectly. For Example if 10 bits were received incorrectly, then a BER reader being implemented by the above procedure will display a maximum error value of 30 in the received signal.

Keywords

Frequency Reader; Bit Error Rate; VHDL; Pseudo Random Sequence; Differential Encoding.

Cite this Article

Sudharsan S. “Stimulation and Hardware Development of Frequency Reader & Bit Error Rate Using VHDL, ”International Journal of Advanced Computing and Communication Systems, pp. 021-028, July, 2017.

Copyright

© 2017 Sudharsan S. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.