International Journal of Advanced Computing and Communication Systems

Area Tradeoff Analysis for Dynamic Scan Low Power DFT Architecture on UltraSPARC T2

John Bedford Solomon, Jackuline Moni, Research Scholar, Karunya University, Coimbatore, TamilNadu, India.

Amar Babu Y, LBRCE, Mylavaram, Andhra Pradesh, India.

International Journal of Advanced Computing and Communication Systems

ISSN (Online) : 2347 - 9299

ISSN (Print) : 2347 - 9280

Received On :

Revised On :

Accepted On :

Published On :

Volume 03, Issue 03

Page No : 018-020

Abstract

In nanometer technology, system on chip integrate 100’s of IP cores and the system becomes more complex to test and reliability becomes a major pain point. As the number of cores increase the power consumption will be the main challenging problem to optimize to get correct functionality from individual cores. To improve observability and controllability designers add extra test overheads that impact system performance in terms of area and power consumption. In this paper a novel dynamic scan low power DFT architecture is proposed to improve observability and controllability at individual core level while optimizing 10% of area on UltraSPARC chip multiprocessor.

Keywords

DFT,System On Chip, Network On Chip, Low Power.

Cite this Article

John Bedford Solomon, Jackuline Moni and Amar Babu Y, “Area Tradeoff Analysis for Dynamic Scan Low Power DFT Architecture on UltraSPARC T2, ”International Journal of Advanced Computing and Communication Systems, pp. 018-020, November, 2016.

Copyright

© 2016 John Bedford Solomon, Jackuline Moni and Amar Babu Y. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.