International Journal of Advanced Computing and Communication Systems

An Improved Power Gating Technique for Low Power Circuits Using Asynchronous Logic

Kavinmalar P, Department of ME VLSI Design, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India.

Jaishankar B, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India.

International Journal of Advanced Computing and Communication Systems

ISSN (Online) : 2347 - 9299

ISSN (Print) : 2347 - 9280

Received On :

Revised On :

Accepted On :

Published On :

Volume 01, Issue 03

Page No : 001-004

Abstract

Power consumption has become a significant concern in the design of digital integrated circuits. It is techniques, power gating is one of the most effective techniques for leakage reduction. Power gating is one of the necessary to provide low power and high performance system. An improved fine grained power gating technique is presented in this paper. This work mainly focused on obtaining low power by implementing asynchronous logic. Asynchronous system design in recent years has reemerged as an important vehicle in the field of high performance, low power and secure computing. It represents an important design methodology in recent deep sub-micron technologies. High leakage current in deep-sub micrometer regimes is becoming a significant contributor to power dissipation as threshold voltage, channel length, and gate oxide thickness are reduced. Power gating is one of the most effective techniques for leakage reduction. In the proposed work, each pipeline stage in the circuit is comprised of logic gates, which implements the logic function and a handshake controller. The power to the logic blocks are controlled and supplied by the handshaking controllers. The work measures and compares the power consumption, area and delay of a 4 bit traditional Array multiplier with the proposed power gated Array multiplier using DSCH tool.

Keywords

Asynchronous logic, power gating, low power.

Cite this Article

Kavinmalar P and Jaishankar B, “An Improved Power Gating Technique for Low Power Circuits Using Asynchronous Logic,” International Journal of Advanced Computing and Communication Systems, pp. 001-004, November, 2014.

Copyright

© 2014 Kavinmalar P and Jaishankar B. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.