International Journal of Advanced Computing and Communication Systems

Fault Classification in Analog Circuits Using Evolutionary Algorithms

Gomathy V and Sumathi S, PSG College of Technology, Coimbatore, Tamil Nadu, India.

International Journal of Advanced Computing and Communication Systems

ISSN (Online) : 2347 - 9299

ISSN (Print) : 2347 - 9280

Received On :

Revised On :

Accepted On :

Published On :

Volume 01, Issue 02

Page No : 008-013

Abstract

Testing of analog electronic circuits for faults has The NN can learn the samples itself according to some training rules and after a training stage it can predict a been challenging due to a myriad of problems such as sample which does not belong to the training samples. Up to unpredictable variation in component tolerance, non-linearity now, the back-propagation neural network (BPNN) was the and lack of mathematical fault models. The fault testing most popular classifier in the analog diagnosis domain, but it procedure can rather be performed using artificial intelligence techniques though, for they are better than mathematical models and automate the testing process altogether. The project proposed seeks to automate fault testing procedure faces some difficulties like easy entrapment into the local minima during the training stage, long training time to convergence and also ANN is sensitive to the data dimension of the training samples. High-dimensional data using support vector machines (SVM) based classifier, a always results in a long training time, and sometimes, widely successful AI model. Consequently, an SVM-based classifier is built and trained for the circuit under test (CUT), which can then on its own autonomy pronounce whether a newly projected state of the circuit is faulty or not. Primarily, the distinguishing features of the many faults that can arise in the CUT are assessed. For these specific features, data corresponding to the several faulty operational states are extracted, here, in P-SPICE software suite using Monte-Carlo technique. Later, three ensemble of SVMs, each of the following strategies – Directed-Acyclic-Graph, Voting and Cascading are built and trained that can now accomplish the classification. The performance of the classifiers thus created failure to converge. Hence we go for support vector classifier, which is characterized by fast convergence to the global optimization, excellent generalization capability and immunity to high-dimensional data.

Keywords

Support Vector Machine, Monte-Carlo Technique, Directed-Acyclic-Graph Strategy, Voting Strategy, Cascading Strategy.

Cite this Article

Gomathy V and Sumathi S, “Fault Classification in Analog Circuits Using Evolutionary Algorithms,” International Journal of Advanced Computing and Communication Systems, pp. 008-013, July, 2014.

Copyright

© 2014 Gomathy V and Sumathi S. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.